Printed Circuit Board Layout

Printed circuit board (PCB) design effort keeps growing as additional constraints such as rising clock frequencies, reduced area, increasing number of layers, mixed signal devices, and the ever increase in component numbers and densities. All of these factors combined have led to a steady rate of increase in development costs for current systems. As we design ever larger, denser and more complex systems, it is becoming increasingly difficult to estimate how much time would be required to design and verify them. To compound this problem, PCB design effort estimation still does not have a quantitative approach. We present in this paper a first step toward creating a design effort metric that is highly correlated with design effort for PCB layout. We follow the same approach taken in [1] as the principles that are applicable to microprocessors are also applicable to PCBs. In this paper, design effort corresponds to the number of engineering-hours required for implementation (layout) of a PCB design.

This paper analyzes and proposes various statistics to estimate the layout effort required to develop PCBs. We investigate and quantify statistics such as area, component count, pin count and device types and sizes for many PCBs. We analyze several of these statistics, and propose a metric, obtained after applying non-linear regression over the different statistics, which we call μPCBComplexity. In addition, we provide insights on the correlation between several statistics and design effort for several known layout design times. Different designs have different constraints, leading to specific challenges; typical design constraints being area, frequency, and cost. For example, having area being a primary design constraint, may lead to a requirement for additional layers, more expensive package types, and more complex placement and routing. A design constrained by cost, on the other hand, may require a balance between number of layers, area, drill density, types of packages and possibly the number of different drill sizes. Having clear constraints is necessary in estimating layout effort as it can drastically affect complexity. We define design effort to be the layout time required by one engineer. Design effort is equivalent to layout time when the project has a single developer, which is frequent even for complex PCBs. Nevertheless, for a given effort requirement, it is possible to reduce the design time by increasing the number of workers. Nevertheless, increasing the number of workers decreases the productivity per worker. The relationship between these two elements has been widely studied in software metrics and business models. Since the conversion between design effort and design time can be approximated, the remainder of this paper focuses only on design effort. The rest of the paper is organized as follows. Section 2 covers other work in this area; Section 3 describes the statistical techniques that allow us to calibrate and evaluate the μPCBComplexity regression model; Section 4 describes the setup for our evaluation; Section 5 evaluates several statistics for the boards in our analysis; and Section 6 presents conclusions and future work.

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